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S1 - Test step one
S2 - Test step two
S3 - Test step three
S4 - Test step four
S5 - Test step five
S6 - Test step six
S7 - Test step seven
S8 - Test step eight
S9 - Test step nine
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•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_V
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž