ChipTest/PAN159/PAN159-Template/Library/StdDriver/driver/lib_driver_pan159.lib

!<arch>
/               0           0     0     0       2540      `
X†††††+Æ+Æ+Æ9®9®9®9®9®	a6	a6	a6	a6	a6	a6††††††††††††††††††††††††††††††††††††ÇŠÇŠÇŠÇŠèVèVèVèVèVzzzzzzzzA:A:A:A:A:A:A:A:A:A:A:g†g†g†g†g†‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z‚Z__asm___23_lib_driver_adc_pan159_c_dd2d65b9____REV16__asm___23_lib_driver_adc_pan159_c_dd2d65b9____REVSHadc_pan159_initadc_pan159_samp1adc_pan159_samp2__delay_pan159__asm___25_lib_driver_delay_pan159_c_ce5cfd0c____REV16__asm___25_lib_driver_delay_pan159_c_ce5cfd0c____REVSH__asm___25_lib_driver_flash_pan159_c_d766fa64____REV16__asm___25_lib_driver_flash_pan159_c_d766fa64____REVSHflash_pan159_eraseflash_pan159_readflash_pan159_write__asm___24_lib_driver_gpio_pan159_c_0a0fc15c____REV16__asm___24_lib_driver_gpio_pan159_c_0a0fc15c____REVSHEINT0_IRQHandlerEINT1_IRQHandlergpio_ext0_int_initgpio_ext1_int_init__asm___23_lib_driver_iic_pan159_c_ae965f01____REV16__asm___23_lib_driver_iic_pan159_c_ae965f01____REVSHg_u8EndFlagg_u8DeviceAddrg_u8RegAddrg_u8DataLeng_u8DataLenMaxs_I2CHandlerFncbk_successcbk_failedbuf_addrI2C0_IRQHandleriic_master_rxiic_master_txiic_pan159_initiic_start_read_bytesiic_start_send_bytesis_iic_busy__asm___23_lib_driver_pwm_pan159_c_c0813419____REV16__asm___23_lib_driver_pwm_pan159_c_c0813419____REVSHpwm_pan159_initpwm_pan159_setDuty__asm___25_lib_driver_rfspi_pan159_c_b0ecd6bb____REV16__asm___25_lib_driver_rfspi_pan159_c_b0ecd6bb____REVSHrfspi_pan159_initrfspi_pan159_rwcrfspi_pan159_rws__asm___25_lib_driver_timer_pan159_c_81fccacb____REV16__asm___25_lib_driver_timer_pan159_c_81fccacb____REVSHDrvTimer0_SetTimerDrvTimer1_SetTimerTMR0_IRQHandlerTMR1_IRQHandlertimer1_pan159_inittimer_pan159_init__asm___24_lib_driver_uart_pan159_c_bb43f66e____REV16__asm___24_lib_driver_uart_pan159_c_bb43f66e____REVSHuartRcvBufferuartTxBufferwptru8InCharu16Countu16TxDataLenUART0_IRQHandleruart_init_pan159uart_send__asm___23_lib_driver_wdt_pan159_c_f9ea1963____REV16__asm___23_lib_driver_wdt_pan159_c_f9ea1963____REVSHDrvWDT_FeedDrvWDT_InitDrvWDT_close__asm___19_lib_driver_xn297l_c_fd081504____REV16__asm___19_lib_driver_xn297l_c_fd081504____REVSHRF_Carrierrf_initxn297l_clear_fifoxn297l_clear_statusxn297l_get_statusxn297l_initxn297l_read_bufxn297l_read_regxn297l_rx_dataxn297l_rx_modexn297l_set_addrxn297l_set_channelxn297l_tx_dataxn297l_tx_modexn297l_write_bufxn297l_write_reg//              0           0     0     0       281       `
lib_driver_adc_pan159.o/
lib_driver_delay_pan159.o/
lib_driver_flash_pan159.o/
lib_driver_gpio_pan159.o/
lib_driver_iic_pan159.o/
lib_driver_pwm_pan159.o/
lib_driver_rfspi_pan159.o/
lib_driver_timer_pan159.o/
lib_driver_uart_pan159.o/
lib_driver_wdt_pan159.o/
lib_driver_xn297l.o/

/0              1633579527  0     0     100666  204804    `
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..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h
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..\\..\\..\\Library\\StdDriver\\driver\\lib_driver_adc_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil__asm___23_lib_driver_adc_pan159_c_dd2d65b9____REVSHdJ







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..\..\..\Library\StdDriver\driver\lib_driver_adc_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\KeilYadc_chns_tableÝYadc_cur_chn_indexÿ
..\..\..\Library\StdDriver\driver\lib_driver_adc_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil*?ÿ

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..\..\..\Library\StdDriver\driver\lib_driver_adc_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil>?Ž
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__DATE__ "Oct  7 2021"
__TIME__ "12:05:27"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 531
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1
"
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¬SCB_ICSR_PENDSTSET_Pos 26U
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¯SCB_ICSR_PENDSTCLR_Pos 25U
°SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
²SCB_ICSR_ISRPREEMPT_Pos 23U
³SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
µSCB_ICSR_ISRPENDING_Pos 22U
¶SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
¸SCB_ICSR_VECTPENDING_Pos 12U
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»SCB_ICSR_VECTACTIVE_Pos 0U
¼SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
¿SCB_AIRCR_VECTKEY_Pos 16U
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ÅSCB_AIRCR_ENDIANESS_Pos 15U
ÆSCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ÈSCB_AIRCR_SYSRESETREQ_Pos 2U
ÉSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
ËSCB_AIRCR_VECTCLRACTIVE_Pos 1U
ÌSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ÏSCB_SCR_SEVONPEND_Pos 4U
ÐSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
ÒSCB_SCR_SLEEPDEEP_Pos 2U
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ÕSCB_SCR_SLEEPONEXIT_Pos 1U
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ÙSCB_CCR_STKALIGN_Pos 9U
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ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
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üSysTick_CTRL_CLKSOURCE_Pos 2U
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..\..\..\Library\CMSIS\Include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil*›!_reserved0Y
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..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


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#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )
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%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )
&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )
'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )
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)TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )
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3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)
4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)
5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)
6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)
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@SYS_MFP_P00_GPIO 0x00000000UL
ASYS_MFP_P00_UART0_nCTS 0x00000100UL
BSYS_MFP_P00_UART0_TXD 0x00000101UL
CSYS_MFP_P00_Msk 0x00000101UL
ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
GSYS_MFP_P01_UART0_nRTS 0x00000200UL
HSYS_MFP_P01_UART0_RXD 0x00000202UL
ISYS_MFP_P01_Msk 0x00000202UL
KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
NSYS_MFP_P04_Msk 0x00001010UL
PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
|SYS_MFP_P15_UART1_TXD 0x00002000UL
}SYS_MFP_P15_Msk 0x00002020UL
SYS_MFP_P22_GPIO 0x00000000UL
€
SYS_MFP_P22_I2C1_SCL 0x00000404UL
�
SYS_MFP_P22_PWM0_CH0 0x00000400UL
‚
SYS_MFP_P22_Msk 0x00000404UL
„
SYS_MFP_P23_GPIO 0x00000000UL
…
SYS_MFP_P23_I2C1_SDA 0x00000808UL
†
SYS_MFP_P23_PWM0_CH1 0x00000800UL
‡
SYS_MFP_P23_Msk 0x00000808UL
‰
SYS_MFP_P24_GPIO 0x00000000UL
Š
SYS_MFP_P24_PWM0_CH2 0x00001000UL
‹
SYS_MFP_P24_UART1_RXD 0x00000010UL
Œ
SYS_MFP_P24_Msk 0x00001010UL
Ž
SYS_MFP_P25_GPIO 0x00000000UL
�
SYS_MFP_P25_PWM0_CH3 0x00002000UL
�
SYS_MFP_P25_UART1_TXD 0x00000020UL
‘
SYS_MFP_P25_Msk 0x00002020UL
“
SYS_MFP_P26_ACMP1_O 0x00004040UL
”
SYS_MFP_P26_GPIO 0x00000000UL
•
SYS_MFP_P26_PWM0_CH4 0x00004000UL
–
SYS_MFP_P26_Msk 0x00004040UL
˜
SYS_MFP_P30_ACMP1_N 0x00000100UL
™
SYS_MFP_P30_ADC_CH6 0x00000101UL
š
SYS_MFP_P30_GPIO 0x00000000UL
›
SYS_MFP_P30_Msk 0x00000101UL
�
SYS_MFP_P31_ACMP1_P0 0x00000200UL
ž
SYS_MFP_P31_ADC_CH7 0x00000202UL
Ÿ
SYS
..\..\..\Library\StdDriver\inc\sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<Ù

¢SYS_UnlockReg<î

´SYS_LockReg
ABC

__CLK_H__ 
"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
€
CLK_PLLCTL_NO_2 0x4000UL
�
CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

EFG

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
IJK

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
MNO

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
QRS

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
UVW

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
YZ[

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
]^_

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


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..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

”
SPI_SET_SS_HIGH$ãspi"¯
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Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
abc

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
…
TIMER_DisableWakeup$âtimer<€
�
TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


efgh

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
<‰
ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
jkl

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
nop

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
rst

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
€
__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
¦]§]¨]
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n







..\..\..\Library\Device\Nuvoton\Mini58Series\Include\..\..\..\Library\CMSIS\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\Library\StdDriver\inc\Mini58Series.h
core_cm0.hsystem_Mini58Series.h
stdint.hsys.hclk.hacmp.hadc.hfmc.hgpio.hi2c.hpwm.hspi.htimer.huart.hwdt.hwwdt.h

4
..\..\..\Library\Device\Nuvoton\Mini58Series\Include\Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
unsigned charunsigned shortunsigned longtáPIRQn_Type5
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&ADC_ENABLE_CH0_P53 0
'ADC_ENABLE_CH1_P10 0
(ADC_ENABLE_CH2_P12 0
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*ADC_ENABLE_CH4_P14 0
+ADC_ENABLE_CH5_P15 0
,ADC_ENABLE_CH6_P30 0
-ADC_ENABLE_CH7_P31 0
/ADC_PAN159_CH0_P53 (1<<0)
0ADC_PAN159_CH1_P10 (1<<1)
1ADC_PAN159_CH2_P12 (1<<2)
2ADC_PAN159_CH3_P13 (1<<3)
3ADC_PAN159_CH4_P14 (1<<4)
4ADC_PAN159_CH5_P15 (1<<5)
5ADC_PAN159_CH6_P30 (1<<6)
6ADC_PAN159_CH7_P31 (1<<7)
<adc_pan159_value() ADC_GET_CONVERSION_DATA(ADC,NULL)
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Input Comments:p1c18-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide lib_driver_adc_pan159.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c -o.\obj\lib_driver_adc_pan159.o --depend=.\obj\lib_driver_adc_pan159.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I..\debug -IC:\Users\Terry\AppData\Local\Arm\Packs\Nuvoton\NuMicro_DFP\1.3.12\Device\Mini58\Include -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=531 --omf_browse=.\obj\lib_driver_adc_pan159.crf ..\..\..\Library\StdDriver\driver\lib_driver_adc_pan159.c|
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..\\..\\..\\Library\\StdDriver\\driver\\lib_driver_delay_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil__asm___25_lib_driver_delay_pan159_c_ce5cfd0c____REVSHdJ







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..\\..\\..\\Library\\StdDriver\\driver\\lib_driver_delay_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil__delay_pan159pY







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..\..\..\Library\StdDriver\driver\lib_driver_delay_pan159.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil\R






..\..\..\Library\StdDriver\driver\lib_driver_delay_pan159.c


__DATE__ "Oct  7 2021"
__TIME__ "12:05:27"
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__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
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__MICROLIB 1
__UVISION_VERSION 531
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__arm__ 1
__TARGET_ARCH_6S_M 1
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__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
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__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1



%

.




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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


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..\..\..\Library\CMSIS\Include\core_cmInstr.h
cmsis_armcc.h


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 !

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..\..\..\Library\CMSIS\Include\core_cmFunc.h
cmsis_armcc.h


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..\..\..\Library\CMSIS\Include\core_cmFunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
#$%

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J__CM0_CMSIS_VERSION_MAIN (0x04U)
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…APSR_N_Pos 31U
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¾xPSR_C_Pos 29U
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ÁxPSR_V_Pos 28U
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ÄxPSR_T_Pos 24U
ÅxPSR_T_Msk (1UL << xPSR_T_Pos)
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¬SCB_ICSR_PENDSTSET_Pos 26U
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¯SCB_ICSR_PENDSTCLR_Pos 25U
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²SCB_ICSR_ISRPREEMPT_Pos 23U
³SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
µSCB_ICSR_ISRPENDING_Pos 22U
¶SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
¸SCB_ICSR_VECTPENDING_Pos 12U
¹SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
»SCB_ICSR_VECTACTIVE_Pos 0U
¼SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
¿SCB_AIRCR_VECTKEY_Pos 16U
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ÂSCB_AIRCR_VECTKEYSTAT_Pos 16U
ÃSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
ÅSCB_AIRCR_ENDIANESS_Pos 15U
ÆSCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ÈSCB_AIRCR_SYSRESETREQ_Pos 2U
ÉSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
ËSCB_AIRCR_VECTCLRACTIVE_Pos 1U
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ÏSCB_SCR_SEVONPEND_Pos 4U
ÐSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
ÒSCB_SCR_SLEEPDEEP_Pos 2U
ÓSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
ÕSCB_SCR_SLEEPONEXIT_Pos 1U
ÖSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
ÙSCB_CCR_STKALIGN_Pos 9U
ÚSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
úSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
üSysTick_CTRL_CLKSOURCE_Pos 2U
ýSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ÿSysTick_CTRL_TICKINT_Pos 1U
€SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
‚SysTick_CTRL_ENABLE_Pos 0U
ƒSysTick_CTRL_ENABLE_Msk (1UL )
†SysTick_LOAD_RELOAD_Pos 0U
‡SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ŠSysTick_VAL_CURRENT_Pos 0U
‹SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ŽSysTick_CALIB_NOREF_Pos 31U
�SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALI
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__SYSTEM_MINI58SERIES_H__ 
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 __HIRC (22118400UL)lb






..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


4

..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keilq__HSIY


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__SYS_H__ 
!ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos )
"ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos )
#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )
$UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )
%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )
&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )
'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )
(I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos )
)TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )
*TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )
+GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )
1SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos)
2SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos)
3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)
4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)
5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)
6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)
<SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
=SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
>SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
@SYS_MFP_P00_GPIO 0x00000000UL
ASYS_MFP_P00_UART0_nCTS 0x00000100UL
BSYS_MFP_P00_UART0_TXD 0x00000101UL
CSYS_MFP_P00_Msk 0x00000101UL
ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
GSYS_MFP_P01_UART0_nRTS 0x00000200UL
HSYS_MFP_P01_UART0_RXD 0x00000202UL
ISYS_MFP_P01_Msk 0x00000202UL
KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
NSYS_MFP_P04_Msk 0x00001010UL
PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
|SYS_MFP_P15_UART1_TXD 0x00002000UL
}SYS_MFP_P15_Msk 0x00002020UL
SYS_MFP_P22_GPIO 0x00000000UL
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SYS_MFP_P22_I2C1_SCL 0x00000404UL
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SYS_MFP_P22_PWM0_CH0 0x00000400UL
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SYS_MFP_P22_Msk 0x00000404UL
„
SYS_MFP_P23_GPIO 0x00000000UL
…
SYS_MFP_P23_I2C1_SDA 0x00000808UL
†
SYS_MFP_P23_PWM0_CH1 0x00000800UL
‡
SYS_MFP_P23_Msk 0x00000808UL
‰
SYS_MFP_P24_GPIO 0x00000000UL
Š
SYS_MFP_P24_PWM0_CH2 0x00001000UL
‹
SYS_MFP_P24_UART1_RXD 0x00000010UL
Œ
SYS_MFP_P24_Msk 0x00001010UL
Ž
SYS_MFP_P25_GPIO 0x00000000UL
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SYS_MFP_P25_PWM0_CH3 0x00002000UL
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SYS_MFP_P25_UART1_TXD 0x00000020UL
‘
SYS_MFP_P25_Msk 0x00002020UL
“
SYS_MFP_P26_ACMP1_O 0x00004040UL
”
SYS_MFP_P26_GPIO 0x00000000UL
•
SYS_MFP_P26_PWM0_CH4 0x00004000UL
–
SYS_MFP_P26_Msk 0x00004040UL
˜
SYS_MFP_P30_ACMP1_N 0x00000100UL
™
SYS_MFP_P30_ADC_CH6 0x00000101UL
š
SYS_MFP_P30_GPIO 0x00000000UL
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SYS_MFP_P30_Msk 0x00000101UL
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SYS_MFP_P31_ACMP1_P0 0x00000200UL
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SYS_MFP_P31_ADC_CH7 0x00000202UL
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SYS
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"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
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CLK_PLLCTL_NO_2 0x4000UL
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CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

456

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
89:

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
<=>

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
@AB

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
DEF

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
HIJ

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
LMN

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


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..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

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SPI_SET_SS_HIGH$ãspi"¯
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Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
PQR

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
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TIMER_DisableWakeup$âtimer<€
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TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


TUVW

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
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ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
YZ[

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
]^_

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
abc

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
€
__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
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core_cm0.hsystem_Mini58Series.h
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ÒSCB_SCR_SLEEPDEEP_Pos 2U
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ÕSCB_SCR_SLEEPONEXIT_Pos 1U
ÖSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
ÙSCB_CCR_STKALIGN_Pos 9U
ÚSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
úSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
üSysTick_CTRL_CLKSOURCE_Pos 2U
ýSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ÿSysTick_CTRL_TICKINT_Pos 1U
€SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
‚SysTick_CTRL_ENABLE_Pos 0U
ƒSysTick_CTRL_ENABLE_Msk (1UL )
†SysTick_LOAD_RELOAD_Pos 0U
‡SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ŠSysTick_VAL_CURRENT_Pos 0U
‹SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ŽSysTick_CALIB_NOREF_Pos 31U
�SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALI
..\..\..\Library\CMSIS\Include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil*›!_reserved0Y
#!VY
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__SYSTEM_MINI58SERIES_H__ 
__XTAL12M (12000000UL)
__XTAL32K (32768UL)
__IRC10K (10000UL)
__XTAL __XTAL12M
__HXT __XTAL
 __HIRC (22118400UL)lb






..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


4

..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keilq__HSIY


qSystemCoreClockY


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CyclesPerUs"
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__SYS_H__ 
!ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos )
"ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos )
#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )
$UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )
%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )
&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )
'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )
(I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos )
)TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )
*TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )
+GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )
1SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos)
2SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos)
3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)
4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)
5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)
6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)
<SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
=SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
>SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
@SYS_MFP_P00_GPIO 0x00000000UL
ASYS_MFP_P00_UART0_nCTS 0x00000100UL
BSYS_MFP_P00_UART0_TXD 0x00000101UL
CSYS_MFP_P00_Msk 0x00000101UL
ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
GSYS_MFP_P01_UART0_nRTS 0x00000200UL
HSYS_MFP_P01_UART0_RXD 0x00000202UL
ISYS_MFP_P01_Msk 0x00000202UL
KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
NSYS_MFP_P04_Msk 0x00001010UL
PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
|SYS_MFP_P15_UART1_TXD 0x00002000UL
}SYS_MFP_P15_Msk 0x00002020UL
SYS_MFP_P22_GPIO 0x00000000UL
€
SYS_MFP_P22_I2C1_SCL 0x00000404UL
�
SYS_MFP_P22_PWM0_CH0 0x00000400UL
‚
SYS_MFP_P22_Msk 0x00000404UL
„
SYS_MFP_P23_GPIO 0x00000000UL
…
SYS_MFP_P23_I2C1_SDA 0x00000808UL
†
SYS_MFP_P23_PWM0_CH1 0x00000800UL
‡
SYS_MFP_P23_Msk 0x00000808UL
‰
SYS_MFP_P24_GPIO 0x00000000UL
Š
SYS_MFP_P24_PWM0_CH2 0x00001000UL
‹
SYS_MFP_P24_UART1_RXD 0x00000010UL
Œ
SYS_MFP_P24_Msk 0x00001010UL
Ž
SYS_MFP_P25_GPIO 0x00000000UL
�
SYS_MFP_P25_PWM0_CH3 0x00002000UL
�
SYS_MFP_P25_UART1_TXD 0x00000020UL
‘
SYS_MFP_P25_Msk 0x00002020UL
“
SYS_MFP_P26_ACMP1_O 0x00004040UL
”
SYS_MFP_P26_GPIO 0x00000000UL
•
SYS_MFP_P26_PWM0_CH4 0x00004000UL
–
SYS_MFP_P26_Msk 0x00004040UL
˜
SYS_MFP_P30_ACMP1_N 0x00000100UL
™
SYS_MFP_P30_ADC_CH6 0x00000101UL
š
SYS_MFP_P30_GPIO 0x00000000UL
›
SYS_MFP_P30_Msk 0x00000101UL
�
SYS_MFP_P31_ACMP1_P0 0x00000200UL
ž
SYS_MFP_P31_ADC_CH7 0x00000202UL
Ÿ
SYS
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¢SYS_UnlockReg9ð

´SYS_LockReg
CDE

__CLK_H__ 
"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
€
CLK_PLLCTL_NO_2 0x4000UL
�
CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
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CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
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GHI

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
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__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
OPQ

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
STU

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
WXY

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
[\]

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
_`a

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


<

..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

”
SPI_SET_SS_HIGH$ãspi"¯
<‰
Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
cde

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
…
TIMER_DisableWakeup$âtimer<€
�
TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


ghij

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
<‰
ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
lmn

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
pqr

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
tuv

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
€
__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
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core_cm0.hsystem_Mini58Series.h
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__DATE__ "Oct  7 2021"
__TIME__ "12:05:28"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 531
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1
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µSCB_ICSR_ISRPENDING_Pos 22U
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¸SCB_ICSR_VECTPENDING_Pos 12U
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ÅSCB_AIRCR_ENDIANESS_Pos 15U
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ÙSCB_CCR_STKALIGN_Pos 9U
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ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
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@SYS_MFP_P00_GPIO 0x00000000UL
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BSYS_MFP_P00_UART0_TXD 0x00000101UL
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ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
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KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
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PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
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SYS_MFP_P26_GPIO 0x00000000UL
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6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
€
CLK_PLLCTL_NO_2 0x4000UL
�
CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

JKL

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
NOP

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
RST

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
VWX

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
Z[\

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


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..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
^_`

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
bcd

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


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..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

”
SPI_SET_SS_HIGH$ãspi"¯
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Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
fgh

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
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TIMER_DisableWakeup$âtimer<€
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TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


jklm

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
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ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
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__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
stu

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
wxy

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
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__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
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core_cm0.hsystem_Mini58Series.h
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..\..\..\Library\CMSIS\Include\core_cmInstr.h
cmsis_armcc.h


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*__CORE_CMFUNC_H 5`U






..\..\..\Library\CMSIS\Include\core_cmFunc.h
cmsis_armcc.h


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*__CORE_CM0_H_GENERIC ,
J__CM0_CMSIS_VERSION_MAIN (0x04U)
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T__INLINE __inline
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…APSR_N_Pos 31U
†APSR_N_Msk (1UL << APSR_N_Pos)
ˆAPSR_Z_Pos 30U
‰APSR_Z_Msk (1UL << APSR_Z_Pos)
‹APSR_C_Pos 29U
ŒAPSR_C_Msk (1UL << APSR_C_Pos)
ŽAPSR_V_Pos 28U
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¸xPSR_N_Pos 31U
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»xPSR_Z_Pos 30U
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¾xPSR_C_Pos 29U
¿xPSR_C_Msk (1UL << xPSR_C_Pos)
ÁxPSR_V_Pos 28U
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ÄxPSR_T_Pos 24U
ÅxPSR_T_Msk (1UL << xPSR_T_Pos)
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“SCB_CPUID_IMPLEMENTER_Pos 24U
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–SCB_CPUID_VARIANT_Pos 20U
—SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
™SCB_CPUID_ARCHITECTURE_Pos 16U
šSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
œSCB_CPUID_PARTNO_Pos 4U
�SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ŸSCB_CPUID_REVISION_Pos 0U
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£SCB_ICSR_NMIPENDSET_Pos 31U
¤SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
¦SCB_ICSR_PENDSVSET_Pos 28U
§SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
©SCB_ICSR_PENDSVCLR_Pos 27U
ªSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
¬SCB_ICSR_PENDSTSET_Pos 26U
­SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
¯SCB_ICSR_PENDSTCLR_Pos 25U
°SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
²SCB_ICSR_ISRPREEMPT_Pos 23U
³SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
µSCB_ICSR_ISRPENDING_Pos 22U
¶SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
¸SCB_ICSR_VECTPENDING_Pos 12U
¹SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
»SCB_ICSR_VECTACTIVE_Pos 0U
¼SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
¿SCB_AIRCR_VECTKEY_Pos 16U
ÀSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ÂSCB_AIRCR_VECTKEYSTAT_Pos 16U
ÃSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
ÅSCB_AIRCR_ENDIANESS_Pos 15U
ÆSCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ÈSCB_AIRCR_SYSRESETREQ_Pos 2U
ÉSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
ËSCB_AIRCR_VECTCLRACTIVE_Pos 1U
ÌSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ÏSCB_SCR_SEVONPEND_Pos 4U
ÐSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
ÒSCB_SCR_SLEEPDEEP_Pos 2U
ÓSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
ÕSCB_SCR_SLEEPONEXIT_Pos 1U
ÖSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
ÙSCB_CCR_STKALIGN_Pos 9U
ÚSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
úSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
üSysTick_CTRL_CLKSOURCE_Pos 2U
ýSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ÿSysTick_CTRL_TICKINT_Pos 1U
€SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
‚SysTick_CTRL_ENABLE_Pos 0U
ƒSysTick_CTRL_ENABLE_Msk (1UL )
†SysTick_LOAD_RELOAD_Pos 0U
‡SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ŠSysTick_VAL_CURRENT_Pos 0U
‹SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ŽSysTick_CALIB_NOREF_Pos 31U
�SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALI
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__XTAL12M (12000000UL)
__XTAL32K (32768UL)
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 __HIRC (22118400UL)lb






..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


4

..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keilq__HSIY


qSystemCoreClockY


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__SYS_H__ 
!ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos )
"ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos )
#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )
$UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )
%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )
&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )
'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )
(I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos )
)TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )
*TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )
+GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )
1SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos)
2SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos)
3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)
4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)
5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)
6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)
<SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
=SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
>SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
@SYS_MFP_P00_GPIO 0x00000000UL
ASYS_MFP_P00_UART0_nCTS 0x00000100UL
BSYS_MFP_P00_UART0_TXD 0x00000101UL
CSYS_MFP_P00_Msk 0x00000101UL
ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
GSYS_MFP_P01_UART0_nRTS 0x00000200UL
HSYS_MFP_P01_UART0_RXD 0x00000202UL
ISYS_MFP_P01_Msk 0x00000202UL
KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
NSYS_MFP_P04_Msk 0x00001010UL
PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
|SYS_MFP_P15_UART1_TXD 0x00002000UL
}SYS_MFP_P15_Msk 0x00002020UL
SYS_MFP_P22_GPIO 0x00000000UL
€
SYS_MFP_P22_I2C1_SCL 0x00000404UL
�
SYS_MFP_P22_PWM0_CH0 0x00000400UL
‚
SYS_MFP_P22_Msk 0x00000404UL
„
SYS_MFP_P23_GPIO 0x00000000UL
…
SYS_MFP_P23_I2C1_SDA 0x00000808UL
†
SYS_MFP_P23_PWM0_CH1 0x00000800UL
‡
SYS_MFP_P23_Msk 0x00000808UL
‰
SYS_MFP_P24_GPIO 0x00000000UL
Š
SYS_MFP_P24_PWM0_CH2 0x00001000UL
‹
SYS_MFP_P24_UART1_RXD 0x00000010UL
Œ
SYS_MFP_P24_Msk 0x00001010UL
Ž
SYS_MFP_P25_GPIO 0x00000000UL
�
SYS_MFP_P25_PWM0_CH3 0x00002000UL
�
SYS_MFP_P25_UART1_TXD 0x00000020UL
‘
SYS_MFP_P25_Msk 0x00002020UL
“
SYS_MFP_P26_ACMP1_O 0x00004040UL
”
SYS_MFP_P26_GPIO 0x00000000UL
•
SYS_MFP_P26_PWM0_CH4 0x00004000UL
–
SYS_MFP_P26_Msk 0x00004040UL
˜
SYS_MFP_P30_ACMP1_N 0x00000100UL
™
SYS_MFP_P30_ADC_CH6 0x00000101UL
š
SYS_MFP_P30_GPIO 0x00000000UL
›
SYS_MFP_P30_Msk 0x00000101UL
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SYS_MFP_P31_ACMP1_P0 0x00000200UL
ž
SYS_MFP_P31_ADC_CH7 0x00000202UL
Ÿ
SYS
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__CLK_H__ 
"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
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CLK_PLLCTL_NO_2 0x4000UL
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CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

]^_

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
abc

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
efg

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
ijk

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
mno

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
qrs

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
uvw

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


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..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

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SPI_SET_SS_HIGH$ãspi"¯
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Ÿ
SPI_SET_SS_LOW$ãspi<¼
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SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
yz{

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
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TIMER_DisableWakeup$âtimer<€
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TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


}~€

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
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ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
‚ƒ„

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
†‡ˆ

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
Š‹Œ

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
€
__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
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core_cm0.hsystem_Mini58Series.h
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�*œ	CTRL¬#LOAD¬#VAL¬#CALIBR#PSysTick_Typeg
ö<Ô	
õNVIC_EnableIRQ$
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€NVIC_DisableIRQ$
IRQn;´

�NVIC_GetPendingIRQY
$
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˜NVIC_SetPendingIRQ$
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£NVIC_ClearPendingIRQ$
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°NVIC_SetPriority$
IRQn$Y
priority;ò
ÈNVIC_GetPriorityY
$
IRQna__resultY

<Œ
ÚNVIC_SystemReset;Å
�SysTick_ConfigY
$Y
ticksa__resultY


/012

__SYSTEM_MINI58SERIES_H__ 
__XTAL12M (12000000UL)
__XTAL32K (32768UL)
__IRC10K (10000UL)
__XTAL __XTAL12M
__HXT __XTAL
 __HIRC (22118400UL)lb






..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


4

..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keilq__HSIY


qSystemCoreClockY


qCyclesPerUsY


qPllClockY


I8
è__HSIöSystemCoreClock
CyclesPerUs"
PllClock
456

__SYS_H__ 
!ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos )
"ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos )
#PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos )
$UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )
%UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )
&SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )
'I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )
(I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos )
)TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )
*TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )
+GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )
1SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos)
2SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos)
3SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos)
4SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos)
5SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos)
6SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos)
<SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
=SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
>SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
@SYS_MFP_P00_GPIO 0x00000000UL
ASYS_MFP_P00_UART0_nCTS 0x00000100UL
BSYS_MFP_P00_UART0_TXD 0x00000101UL
CSYS_MFP_P00_Msk 0x00000101UL
ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
GSYS_MFP_P01_UART0_nRTS 0x00000200UL
HSYS_MFP_P01_UART0_RXD 0x00000202UL
ISYS_MFP_P01_Msk 0x00000202UL
KSYS_MFP_P04_GPIO 0x00000000UL
LSYS_MFP_P04_PWM0_CH5 0x00001010UL
MSYS_MFP_P04_SPI0_SS 0x00001000UL
NSYS_MFP_P04_Msk 0x00001010UL
PSYS_MFP_P05_GPIO 0x00000000UL
QSYS_MFP_P05_PWM0_CH4 0x00002020UL
RSYS_MFP_P05_SPI0_MOSI 0x00002000UL
SSYS_MFP_P05_Msk 0x00002020UL
USYS_MFP_P06_GPIO 0x00000000UL
VSYS_MFP_P06_PWM0_CH1 0x00004040UL
WSYS_MFP_P06_SPI0_MISO 0x00004000UL
XSYS_MFP_P06_Msk 0x00004040UL
ZSYS_MFP_P07_GPIO 0x00000000UL
[SYS_MFP_P07_PWM0_CH0 0x00008080UL
\SYS_MFP_P07_SPI0_CLK 0x00008000UL
]SYS_MFP_P07_Msk 0x00008080UL
_SYS_MFP_P10_ACMP0_P1 0x00000101UL
`SYS_MFP_P10_ADC_CH1 0x00000001UL
aSYS_MFP_P10_GPIO 0x00000000UL
bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
eSYS_MFP_P12_ADC_CH2 0x00000004UL
fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
hSYS_MFP_P12_PWM0_CH0 0x04000000UL
iSYS_MFP_P12_Msk 0x04000404UL
kSYS_MFP_P13_ACMP0_P3 0x00000808UL
lSYS_MFP_P13_ADC_CH3 0x00000008UL
mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
oSYS_MFP_P13_PWM0_CH1 0x08000000UL
pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
wSYS_MFP_P14_Msk 0x10001010UL
ySYS_MFP_P15_ACMP0_P0 0x00002020UL
zSYS_MFP_P15_ADC_CH5 0x00000020UL
{SYS_MFP_P15_GPIO 0x00000000UL
|SYS_MFP_P15_UART1_TXD 0x00002000UL
}SYS_MFP_P15_Msk 0x00002020UL
SYS_MFP_P22_GPIO 0x00000000UL
€
SYS_MFP_P22_I2C1_SCL 0x00000404UL
�
SYS_MFP_P22_PWM0_CH0 0x00000400UL
‚
SYS_MFP_P22_Msk 0x00000404UL
„
SYS_MFP_P23_GPIO 0x00000000UL
…
SYS_MFP_P23_I2C1_SDA 0x00000808UL
†
SYS_MFP_P23_PWM0_CH1 0x00000800UL
‡
SYS_MFP_P23_Msk 0x00000808UL
‰
SYS_MFP_P24_GPIO 0x00000000UL
Š
SYS_MFP_P24_PWM0_CH2 0x00001000UL
‹
SYS_MFP_P24_UART1_RXD 0x00000010UL
Œ
SYS_MFP_P24_Msk 0x00001010UL
Ž
SYS_MFP_P25_GPIO 0x00000000UL
�
SYS_MFP_P25_PWM0_CH3 0x00002000UL
�
SYS_MFP_P25_UART1_TXD 0x00000020UL
‘
SYS_MFP_P25_Msk 0x00002020UL
“
SYS_MFP_P26_ACMP1_O 0x00004040UL
”
SYS_MFP_P26_GPIO 0x00000000UL
•
SYS_MFP_P26_PWM0_CH4 0x00004000UL
–
SYS_MFP_P26_Msk 0x00004040UL
˜
SYS_MFP_P30_ACMP1_N 0x00000100UL
™
SYS_MFP_P30_ADC_CH6 0x00000101UL
š
SYS_MFP_P30_GPIO 0x00000000UL
›
SYS_MFP_P30_Msk 0x00000101UL
�
SYS_MFP_P31_ACMP1_P0 0x00000200UL
ž
SYS_MFP_P31_ADC_CH7 0x00000202UL
Ÿ
SYS
..\..\..\Library\StdDriver\inc\sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil9Ú

¢SYS_UnlockReg9ð

´SYS_LockReg
89:

__CLK_H__ 
"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
€
CLK_PLLCTL_NO_2 0x4000UL
�
CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

<=>

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
@AB

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
DEF

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
HIJ

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
LMN

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
PQR

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
TUV

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


<

..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

”
SPI_SET_SS_HIGH$ãspi"¯
<‰
Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
XYZ

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
…
TIMER_DisableWakeup$âtimer<€
�
TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


\]^_

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
<‰
ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
abc

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
efg

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


Ä
..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
ijk

6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
€
__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
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..\..\..\Library\Device\Nuvoton\Mini58Series\Include\..\..\..\Library\CMSIS\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\Library\StdDriver\inc\Mini58Series.h
core_cm0.hsystem_Mini58Series.h
stdint.hsys.hclk.hacmp.hadc.hfmc.hgpio.hi2c.hpwm.hspi.htimer.huart.hwdt.hwwdt.h

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..\..\..\Library\Device\Nuvoton\Mini58Series\Include\Mini58Series.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
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__LIB_DIRVER_PWM_PAN159_H !
#__PWM_PAN159_PORT(P) ((P)<<6)
$__PWM_PAN159_PIN(B) ((B)<<3)
%__PWM_PAN159_CHN(C) ((C)<<0)
'PWM_PAN159_PWM0_CH0_P12 (__PWM_PAN159_CHN(0)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(2))
(PWM_PAN159_PWM0_CH0_P22 (__PWM_PAN159_CHN(0)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(2))
)PWM_PAN159_PWM0_CH1_P13 (__PWM_PAN159_CHN(1)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(3))
*PWM_PAN159_PWM0_CH1_P23 (__PWM_PAN159_CHN(1)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(3))
+PWM_PAN159_PWM0_CH2_P24 (__PWM_PAN159_CHN(2)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(4))
,PWM_PAN159_PWM0_CH3_P25 (__PWM_PAN159_CHN(3)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(5))
-PWM_PAN159_PWM0_CH4_P14 (__PWM_PAN159_CHN(4)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(4))
.PWM_PAN159_PWM0_CH4_P26 (__PWM_PAN159_CHN(4)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(6))
/PWM_PAN159_PWM0_CH5_P04 (__PWM_PAN159_CHN(5)|__PWM_PAN159_PORT(0)|__PWM_PAN159_PIN(4))
1PWM_PAN159_PORT_MSK __PWM_PAN159_PORT(0x03)
2PWM_PAN159_PIN_MSK __PWM_PAN159_PIN(0x07)
3PWM_PAN159_CHN_MSK __PWM_PAN159_CHN(0x07)
5PWM_PAN159_PORT(PWMx) ((PWMx)>>6)
6PWM_PAN159_PIN(PWMx) (((PWMx)&PWM_PAN159_PIN_MSK)>>3)
7PWM_PAN159_CHN(PWMx) ((PWMx)&PWM_PAN159_CHN_MSK)
9PWM_PAN159_CMPDAT ((volatile uint32_t*)(0x40040000+0x24))
:PWM_PAN159_OEN (*(volatile uint32_t*)(0x40040000+0x5C))
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Input Comments:p26f8-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide lib_driver_pwm_pan159.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c -o.\obj\lib_driver_pwm_pan159.o --depend=.\obj\lib_driver_pwm_pan159.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I..\debug -IC:\Users\Terry\AppData\Local\Arm\Packs\Nuvoton\NuMicro_DFP\1.3.12\Device\Mini58\Include -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=531 --omf_browse=.\obj\lib_driver_pwm_pan159.crf ..\..\..\Library\StdDriver\driver\lib_driver_pwm_pan159.cÊ
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__DATE__ "Oct  7 2021"
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__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 531
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
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__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
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ESYS_MFP_P01_GPIO 0x00000000UL
FSYS_MFP_P01_SPI0_SS 0x00000002UL
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bSYS_MFP_P10_Msk 0x00000101UL
dSYS_MFP_P12_ACMP0_P2 0x00000404UL
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fSYS_MFP_P12_GPIO 0x00000000UL
gSYS_MFP_P12_UART0_RXD 0x00000400UL
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kSYS_MFP_P13_ACMP0_P3 0x00000808UL
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mSYS_MFP_P13_GPIO 0x00000000UL
nSYS_MFP_P13_UART0_TXD 0x00000800UL
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pSYS_MFP_P13_Msk 0x08000808UL
rSYS_MFP_P14_ACMP0_N 0x00001010UL
sSYS_MFP_P14_ADC_CH4 0x00000010UL
tSYS_MFP_P14_GPIO 0x00000000UL
uSYS_MFP_P14_UART1_RXD 0x00001000UL
vSYS_MFP_P14_PWM0_CH4 0x10000000UL
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zSYS_MFP_P15_ADC_CH5 0x00000020UL
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SYS_MFP_P30_Msk 0x00000101UL
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SYS_MFP_P31_ACMP1_P0 0x00000200UL
ž
SYS_MFP_P31_ADC_CH7 0x00000202UL
Ÿ
SYS
..\..\..\Library\StdDriver\inc\sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<Ù

¢SYS_UnlockReg<î

´SYS_LockReg
>?@

__CLK_H__ 
"FREQ_25MHZ 25000000
#FREQ_50MHZ 50000000
$FREQ_72MHZ 72000000
%FREQ_100MHZ 100000000
&FREQ_200MHZ 200000000
'FREQ_250MHZ 250000000
(FREQ_500MHZ 500000000
.CLK_PWRCTL_XTL12M 0x01UL
/CLK_PWRCTL_XTLEN_HXT 0x01UL
0CLK_PWRCTL_XTL32K 0x02UL
1CLK_PWRCTL_XTLEN_LXT 0x02UL
6CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
7CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
8CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
9CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
:CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
;CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
<CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
=CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
>CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
?CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
@CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
ECLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
FCLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
GCLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
HCLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
ICLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
JCLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
KCLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
LCLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
MCLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
NCLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
OCLK_CLKSEL1_SPISEL_PLL 0x00000020UL
PCLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
QCLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
RCLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
SCLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
TCLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
UCLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
VCLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
WCLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
XCLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
YCLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
ZCLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
[CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
\CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
]CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
^CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
dCLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
eCLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
fCLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
gCLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
hCLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
iCLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
jCLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
kCLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
lCLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
rCLK_CLKDIV_ADC(x) (((x)-1) << 16)
sCLK_CLKDIV_UART(x) (((x)-1) << 8)
tCLK_CLKDIV_HCLK(x) ((x)-1)
yCLK_PLLCTL_PLLSRC_HXT 0x00000000UL
zCLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
|CLK_PLLCTL_NF(x) ((x)-2)
}CLK_PLLCTL_NR(x) (((x)-2)<<9)
CLK_PLLCTL_NO_1 0x0000UL
€
CLK_PLLCTL_NO_2 0x4000UL
�
CLK_PLLCTL_NO_4 0xC000UL
ƒ
CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
„
CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
…
CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
‡
CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
ˆ
CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
‰
CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
Ž
MODULE_APBCLK(x) ((x >>31) & 0x1)
�
MODULE_CLKSEL(x) ((x >>29) & 0x3)
�
MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
‘
MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
’
MODULE_CLKDIV(x) ((x >>18) & 0x3)
“
MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
”
MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
•
MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
–
MODULE_NoMsk 0x0
—
NA MODULE_NoMsk
™
MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
š
MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
›
MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
œ
MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
�
MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
ž
MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
Ÿ
MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
 
MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
¤
ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20
..\..\..\Library\StdDriver\inc\clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil;Þ
Ä
CLK_GetPLLClockFreqY
a__resultY

\u32PllFreqY
\u32PllRegY
\u32FINY
\u32NFY
\u32NRY
\u32NOY
Ð:

\au8NoTblE

BCD

__ACMP_H__ 
!ACMP_VNEG_PIN (0xFFUL)
"ACMP_VNEG_BANDGAP (0x00UL)
#ACMP_VNEG_4_OVER_24_VDD (0x80UL)
$ACMP_VNEG_5_OVER_24_VDD (0x81UL)
%ACMP_VNEG_6_OVER_24_VDD (0x82UL)
&ACMP_VNEG_7_OVER_24_VDD (0x83UL)
'ACMP_VNEG_8_OVER_24_VDD (0x84UL)
(ACMP_VNEG_9_OVER_24_VDD (0x85UL)
)ACMP_VNEG_10_OVER_24_VDD (0x86UL)
*ACMP_VNEG_11_OVER_24_VDD (0x87UL)
+ACMP_VNEG_12_OVER_24_VDD (0x88UL)
,ACMP_VNEG_13_OVER_24_VDD (0x89UL)
-ACMP_VNEG_14_OVER_24_VDD (0x8AUL)
.ACMP_VNEG_15_OVER_24_VDD (0x8BUL)
/ACMP_VNEG_16_OVER_24_VDD (0x8CUL)
0ACMP_VNEG_17_OVER_24_VDD (0x8DUL)
1ACMP_VNEG_18_OVER_24_VDD (0x8EUL)
2ACMP_VNEG_19_OVER_24_VDD (0x8FUL)
3ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos)
4ACMP_HYSTERESIS_DISABLE (0UL)
5ACMP_CH0_POSPIN_P15 (0UL)
6ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos)
7ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos)
8ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos)
9ACMP_CH1_POSPIN_P31 (0UL)
:ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos)
;ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos)
<ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos)
=ACMP_FILTSEL_OFF (0UL)
>ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos)
?ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos)
@ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos)
AACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos)
BACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos)
CACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos)
DACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos)
EACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos)
FACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos)
GACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos)
lACMP_SET_NEG_SRC(acmp,u32ChNum,u32Src) do{ if(u32Src == ACMP_VNEG_PIN) ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk; else { ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk; ACMP->VREF = u32Src; } }while(0)
|ACMP_ENABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
…
ACMP_DISABLE_HYSTERESIS(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
Ž
ACMP_ENABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
—
ACMP_DISABLE_INT(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
¡
ACMP_ENABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
ª
ACMP_DISABLE(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
³
ACMP_GET_OUTPUT(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
¼
ACMP_GET_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
Å
ACMP_CLR_INT_FLAG(acmp,u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
Ó
ACMP_SELECT_P(acmp,u32ChNum,u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
ë
ACMP_CRV_SEL(acmp,u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
ò
ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
ù
ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
‚ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
‹ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
”ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
�ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp,u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
²ACMP_SET_FILTER(acmp,u32ChNum,u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))H=






..\..\..\Library\StdDriver\inc\acmp.h


Ä
..\..\..\Library\StdDriver\inc\acmp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
FGH

__ADC_H__ 
 ADC_CH7_EXT (0UL)
!ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk)
"ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
$ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
%ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
&ADC_TRIGGER_BY_EXT_PIN (0UL)
'ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
(ADC_FALLING_EDGE_TRIGGER (0UL)
)ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
*ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
+ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
,ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
-ADC_SAMPLE_CLOCK_0 (0UL)
.ADC_SAMPLE_CLOCK_1 (1UL)
/ADC_SAMPLE_CLOCK_2 (2UL)
0ADC_SAMPLE_CLOCK_4 (3UL)
1ADC_SAMPLE_CLOCK_8 (4UL)
2ADC_SAMPLE_CLOCK_16 (5UL)
3ADC_SAMPLE_CLOCK_32 (6UL)
4ADC_SAMPLE_CLOCK_64 (7UL)
5ADC_SAMPLE_CLOCK_128 (8UL)
6ADC_SAMPLE_CLOCK_256 (9UL)
7ADC_SAMPLE_CLOCK_512 (10UL)
8ADC_SAMPLE_CLOCK_1024 (11UL)
9ADC_SEQMODE_TYPE_23SHUNT (0UL)
:ADC_SEQMODE_TYPE_1SHUNT (1UL)
;ADC_SEQMODE_MODESELECT_CH01 (0UL)
<ADC_SEQMODE_MODESELECT_CH12 (1UL)
=ADC_SEQMODE_MODESELECT_CH02 (2UL)
>ADC_SEQMODE_PWM0_RISING (0UL)
?ADC_SEQMODE_PWM0_CENTER (1UL)
@ADC_SEQMODE_PWM0_FALLING (2UL)
AADC_SEQMODE_PWM0_PERIOD (3UL)
BADC_SEQMODE_PWM2_RISING (4UL)
CADC_SEQMODE_PWM2_CENTER (5UL)
DADC_SEQMODE_PWM2_FALLING (6UL)
EADC_SEQMODE_PWM2_PERIOD (7UL)
FADC_SEQMODE_PWM4_RISING (8UL)
GADC_SEQMODE_PWM4_CENTER (9UL)
HADC_SEQMODE_PWM4_FALLING (10UL)
IADC_SEQMODE_PWM4_PERIOD (11UL)
\ADC_CONFIG_CH7(adc,u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
eADC_GET_CONVERSION_DATA(adc,u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
qADC_GET_INT_FLAG(adc,u32Mask) ((adc)->STATUS & (u32Mask))
}ADC_CLR_INT_FLAG(adc,u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | ADC_STATUS_ADCMPF0_Msk | ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
‰
ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
”
ADC_IS_DATA_OVERRUN(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
Ÿ
ADC_IS_DATA_VALID(adc,u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
§
ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
¯
ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
À
ADC_ENABLE_CMP0(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP0_CMPDAT_Pos) | (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) | ADC_CMP0_ADCMPIE_Msk | ADC_CMP0_ADCMPEN_Msk)
Ð
ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
á
ADC_ENABLE_CMP1(adc,u32ChNum,u32Condition,u32Data,u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | (u32Condition) | ((u32Data) << ADC_CMP1_CMPDAT_Pos) | ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) | ADC_CMP1_ADCMPEN_Msk)
ð
ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
û
ADC_SET_INPUT_CHANNEL(adc,u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
ƒADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
‹ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)H<






..\..\..\Library\StdDriver\inc\adc.h


À
..\..\..\Library\StdDriver\inc\adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
JKL

__FMC_H__ 
!FMC_APROM_BASE 0x00000000UL
"FMC_APROM_END 0x00008000UL
#FMC_LDROM_BASE 0x00100000UL
$FMC_LDROM_END 0x00100A00UL
%FMC_SPROM_BASE 0x00200000UL
&FMC_SPROM_END 0x00200200UL
'FMC_CONFIG_BASE 0x00300000UL
)FMC_FLASH_PAGE_SIZE 0x200
*FMC_LDROM_SIZE 0xA00
+FMC_SPROM_SIZE 0x200
1FMC_ISPCMD_READ 0x00
2FMC_ISPCMD_READ_UID 0x04
3FMC_ISPCMD_READ_CID 0x0B
4FMC_ISPCMD_READ_PID 0x0C
5FMC_ISPCMD_READ_CRC32 0x0D
6FMC_ISPCMD_PROGRAM 0x21
7FMC_ISPCMD_PAGE_ERASE 0x22
8FMC_ISPCMD_CAL_CRC32 0x2D
9FMC_ISPCMD_VECMAP 0x2E
BFMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
CFMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
DFMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
EFMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)
FFMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
GFMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
HFMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
IFMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
JFMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk)
KFMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
LFMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
MFMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk)
NFMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0)H<






..\..\..\Library\StdDriver\inc\fmc.h


À
..\..\..\Library\StdDriver\inc\fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
NOP

__GPIO_H__ 
GPIO_PIN_MAX 8
$GPIO_MODE_INPUT 0x0UL
%GPIO_MODE_OUTPUT 0x1UL
&GPIO_MODE_OPEN_DRAIN 0x2UL
'GPIO_MODE_QUASI 0x3UL
,GPIO_INT_RISING 0x00010000UL
-GPIO_INT_FALLING 0x00000001UL
.GPIO_INT_BOTH_EDGE 0x00010001UL
/GPIO_INT_HIGH 0x01010000UL
0GPIO_INT_LOW 0x01000001UL
5GPIO_INTTYPE_EDGE 0UL
6GPIO_INTTYPE_LEVEL 1UL
;GPIO_DBCTL_ICLK_ON 0x00000020UL
<GPIO_DBCTL_ICLK_OFF 0x00000000UL
>GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL
?GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL
AGPIO_DBCTL_DBCLKSEL_1 0x00000000UL
BGPIO_DBCTL_DBCLKSEL_2 0x00000001UL
CGPIO_DBCTL_DBCLKSEL_4 0x00000002UL
DGPIO_DBCTL_DBCLKSEL_8 0x00000003UL
EGPIO_DBCTL_DBCLKSEL_16 0x00000004UL
FGPIO_DBCTL_DBCLKSEL_32 0x00000005UL
GGPIO_DBCTL_DBCLKSEL_64 0x00000006UL
HGPIO_DBCTL_DBCLKSEL_128 0x00000007UL
IGPIO_DBCTL_DBCLKSEL_256 0x00000008UL
JGPIO_DBCTL_DBCLKSEL_512 0x00000009UL
KGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL
LGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL
MGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL
NGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL
OGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL
PGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL
`GPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
aP00 GPIO_PIN_ADDR(0, 0)
bP01 GPIO_PIN_ADDR(0, 1)
cP02 GPIO_PIN_ADDR(0, 2)
dP03 GPIO_PIN_ADDR(0, 3)
eP04 GPIO_PIN_ADDR(0, 4)
fP05 GPIO_PIN_ADDR(0, 5)
gP06 GPIO_PIN_ADDR(0, 6)
hP07 GPIO_PIN_ADDR(0, 7)
iP10 GPIO_PIN_ADDR(1, 0)
jP11 GPIO_PIN_ADDR(1, 1)
kP12 GPIO_PIN_ADDR(1, 2)
lP13 GPIO_PIN_ADDR(1, 3)
mP14 GPIO_PIN_ADDR(1, 4)
nP15 GPIO_PIN_ADDR(1, 5)
oP16 GPIO_PIN_ADDR(1, 6)
pP17 GPIO_PIN_ADDR(1, 7)
qP20 GPIO_PIN_ADDR(2, 0)
rP21 GPIO_PIN_ADDR(2, 1)
sP22 GPIO_PIN_ADDR(2, 2)
tP23 GPIO_PIN_ADDR(2, 3)
uP24 GPIO_PIN_ADDR(2, 4)
vP25 GPIO_PIN_ADDR(2, 5)
wP26 GPIO_PIN_ADDR(2, 6)
xP27 GPIO_PIN_ADDR(2, 7)
yP30 GPIO_PIN_ADDR(3, 0)
zP31 GPIO_PIN_ADDR(3, 1)
{P32 GPIO_PIN_ADDR(3, 2)
|P33 GPIO_PIN_ADDR(3, 3)
}P34 GPIO_PIN_ADDR(3, 4)
~P35 GPIO_PIN_ADDR(3, 5)
P36 GPIO_PIN_ADDR(3, 6)
€
P37 GPIO_PIN_ADDR(3, 7)
�
P40 GPIO_PIN_ADDR(4, 0)
‚
P41 GPIO_PIN_ADDR(4, 1)
ƒ
P42 GPIO_PIN_ADDR(4, 2)
„
P43 GPIO_PIN_ADDR(4, 3)
…
P44 GPIO_PIN_ADDR(4, 4)
†
P45 GPIO_PIN_ADDR(4, 5)
‡
P46 GPIO_PIN_ADDR(4, 6)
ˆ
P47 GPIO_PIN_ADDR(4, 7)
‰
P50 GPIO_PIN_ADDR(5, 0)
Š
P51 GPIO_PIN_ADDR(5, 1)
‹
P52 GPIO_PIN_ADDR(5, 2)
Œ
P53 GPIO_PIN_ADDR(5, 3)
�
P54 GPIO_PIN_ADDR(5, 4)
Ž
P55 GPIO_PIN_ADDR(5, 5)
 
GPIO_CLR_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC = u32PinMask)
¬
GPIO_DISABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
¸
GPIO_ENABLE_DEBOUNCE(gpio,u32PinMask) ((gpio)->DBEN |= u32PinMask)
Ä
GPIO_DISABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
Ð
GPIO_ENABLE_DIGITAL_PATH(gpio,u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
Ü
GPIO_DISABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
è
GPIO_ENABLE_DOUT_MASK(gpio,u32PinMask) ((gpio)->DATMSK |= u32PinMask)
õ
GPIO_GET_INT_FLAG(gpio,u32PinMask) ((gpio)->INTSRC & u32PinMask)
‰GPIO_SET_DEBOUNCE_TIME(clksrc,clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
”GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
 GPIO_SET_OUT_DATA(gpio,data) ((gpio)->DOUT = (data))
«GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
¹GPIO_EnableEINT0 GPIO_EnableInt
ÆGPIO_DisableEINT0 GPIO_DisableInt
ÕGPIO_EnableEINT1 GPIO_EnableInt
âGPIO_DisableEINT1 GPIO_DisableIntH=






..\..\..\Library\StdDriver\inc\gpio.h


Ä
..\..\..\Library\StdDriver\inc\gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
RST

__I2C_H__ 
!I2C_STA 0x20
"I2C_STO 0x10
#I2C_SI 0x08
$I2C_AA 0x04
3I2C_SET_CONTROL_REG(i2c,u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
:I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
AI2C_STOP(i2c) do { (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); while((i2c)->CTL & I2C_CTL_STO_Msk); } while(0)
LI2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
SI2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
ZI2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
aI2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
hI2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
oI2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
vI2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
}I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
„
I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
‹
I2C_GET_DATA(i2c) ( (i2c)->DAT )
“
I2C_SET_DATA(i2c,u8Data) ( (i2c)->DAT = u8Data )
š
I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
£
I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
¬
I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
³
I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )H<






..\..\..\Library\StdDriver\inc\i2c.h


À
..\..\..\Library\StdDriver\inc\i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
VWX

__PWM_H__ 
PWM_CHANNEL_NUM (6)
 PWM_CLK_DIV_1 (4UL)
!PWM_CLK_DIV_2 (0UL)
"PWM_CLK_DIV_4 (1UL)
#PWM_CLK_DIV_8 (2UL)
$PWM_CLK_DIV_16 (3UL)
%PWM_EDGE_ALIGNED (0UL)
&PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk)
'PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk
(PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk
)PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk
*PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk
+PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk)
,PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk)
-PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk)
.PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk)
/PWM_PERIOD_INT_UNDERFLOW (0)
0PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk)
4PWM_CH0 0x0
5PWM_CH1 0x1
6PWM_CH2 0x2
7PWM_CH3 0x3
8PWM_CH4 0x4
9PWM_CH5 0x5
HPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
PPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
XPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
`PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
hPWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
pPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
zPWM_ENABLE_OUTPUT_INVERTER(pwm,u32ChannelMask) do{ int i; (pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk); for(i = 0; i < 6; i++) { if((u32ChannelMask) & (1 << i)) (pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); } }while(0)
Ž
PWM_SET_PRESCALER(pwm,u32ChannelNum,u32Prescaler) ((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
ž
PWM_SET_DIVIDER(pwm,u32ChannelNum,u32Divider) ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
ª
PWM_SET_CMR(pwm,u32ChannelNum,u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
¶
PWM_SET_CNR(pwm,u32ChannelNum,u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
Á
PWM_SET_CMRD(pwm,u32ChannelNum,u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
Í
PWM_SET_ALIGNED_TYPE(pwm,u32ChannelMask,u32AlignedType) ((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
Ö
PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
Þ
PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)H<






..\..\..\Library\StdDriver\inc\pwm.h


À
..\..\..\Library\StdDriver\inc\pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
Z[\

__SPI_H__ 
 SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
!SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
"SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
#SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
%SPI_SLAVE (SPI_CTL_SLAVE_Msk)
&SPI_MASTER (0x0)
(SPI_SS (SPI_SSCTL_SS_Msk)
)SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
*SPI_SS_ACTIVE_LOW (0x0)
,SPI_IE_MASK (0x01)
-SPI_SSTA_INTEN_MASK (0x04)
.SPI_FIFO_TX_INTEN_MASK (0x08)
/SPI_FIFO_RX_INTEN_MASK (0x10)
0SPI_FIFO_RXOV_INTEN_MASK (0x20)
1SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
@SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
GSPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
NSPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
USPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
\SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
cSPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
lSPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
uSPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
~SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
…
SPI_READ_RX(spi) ( (spi)->RX )
�
SPI_WRITE_TX(spi,u32TxData) ( (spi)->TX = u32TxData )
¬
SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
³
SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
»
SPI_SET_SUSPEND_CYCLE(spi,u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
Â
SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
É
SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
à
SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
ç
SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )H<






..\..\..\Library\StdDriver\inc\spi.h


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..\..\..\Library\StdDriver\inc\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ã

”
SPI_SET_SS_HIGH$ãspi"¯
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Ÿ
SPI_SET_SS_LOW$ãspi<¼
Ñ
SPI_SET_DATA_WIDTH$ãspi$Y
u32Width
^_`

__TIMER_H__ 
 TIMER_ONESHOT_MODE (0UL)
!TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos)
"TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos)
#TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos)
$TIMER_CAPTURE_FREE_COUNTING_MODE (0UL)
%TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk)
&TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk)
'TIMER_CAPTURE_FALLING_EDGE (0UL)
(TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos)
)TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos)
*TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos)
+TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk)
,TIMER_COUNTER_FALLING_EDGE (0UL)
-TIMER_TOGGLE_TMX_CNT_OUT (0UL)
.TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk)
>TIMER_SET_CMP_VALUE(timer,u32Value) ((timer)->CMP = (u32Value))
HTIMER_SET_PRESCALE_VALUE(timer,u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
RTIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
]TIMER_SELECT_TOUT_PIN(timer,u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))H>






..\..\..\Library\StdDriver\inc\timer.h


\
..\..\..\Library\StdDriver\inc\timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<â

fTIMER_Start$âtimer"Ë
<…
pTIMER_Stop$âtimer<ª
{TIMER_EnableWakeup$âtimer<Ñ
…
TIMER_DisableWakeup$âtimer<€
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TIMER_EnableCaptureDebounce$âtimer<°
š
TIMER_DisableCaptureDebounce$âtimer<ä
¥
TIMER_EnableEventCounterDebounce$âtimer<™
¯
TIMER_DisableEventCounterDebounce$âtimer<¼
¹
TIMER_EnableInt$âtimer<à
Ã
TIMER_DisableInt$âtimer<Š
Í
TIMER_EnableCaptureInt$âtimer<µ
×
TIMER_DisableCaptureInt$âtimer;î
ã
TIMER_GetIntFlagY
$âtimera__resultY

<”
í
TIMER_ClearIntFlag$âtimer;Ô
ù
TIMER_GetCaptureIntFlagY
$âtimera__resultY

<�
ƒTIMER_ClearCaptureIntFlag$âtimer;½
�TIMER_GetWakeupFlagY
$âtimera__resultY

<æ
™TIMER_ClearWakeupFlag$âtimer;£
£TIMER_GetCaptureDataY
$âtimera__resultY

;Ü
­TIMER_GetCounterY
$âtimera__resultY


bcde

__UART_H__ 
$UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos)
%UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos)
&UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos)
'UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos)
)UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos)
*UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos)
+UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos)
,UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos)
1UART_WORD_LEN_5 (0)
2UART_WORD_LEN_6 (1)
3UART_WORD_LEN_7 (2)
4UART_WORD_LEN_8 (3)
6UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos)
7UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos)
8UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos)
9UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos)
:UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos)
<UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos)
=UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos)
>UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos)
DUART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos)
EUART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos)
JUART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos)
KUART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos)
LUART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos)
^UART_BAUD_MODE0 (0)
hUART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
tUART_BAUD_MODE0_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
~UART_BAUD_MODE2_DIVIDER(u32SrcFreq,u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
‰
UART_WRITE(uart,u8Data) (uart->DAT = (u8Data))
’
UART_READ(uart) (uart->DAT)
œ
UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
¦
UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
¯
UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
¹
UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
Ä
UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
Ð
UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
Ü
UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
æ
UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
ð
UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
ƒUART_ENABLE_INT(uart,u32eIntSel) (uart->INTEN |= (u32eIntSel))
•UART_DISABLE_INT(uart,u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
¯UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
ÏUART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
ØUART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)H=






..\..\..\Library\StdDriver\inc\uart.h




..\..\..\Library\StdDriver\inc\uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil<ä

¸UART_CLEAR_RTS
$äuart"Û
<‰
ÄUART_SET_RTS
$äuart2
ÃUART_CLEAR_RTSêUART_SET_RTS
ghi

__WDT_H__ 
WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos)
 WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos)
!WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos)
"WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos)
#WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos)
$WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos)
%WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos)
&WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos)
(WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos)
)WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos)
*WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos)
+WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos)
9WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
?WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
NWDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
WWDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
`WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
hWDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)H<






..\..\..\Library\StdDriver\inc\wdt.h


À
..\..\..\Library\StdDriver\inc\wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
klm

__WWDT_H__ 
WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos)
 WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos)
!WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos)
"WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos)
#WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos)
$WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos)
%WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos)
&WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos)
'WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos)
(WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos)
)WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos)
*WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos)
+WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos)
,WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos)
-WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos)
.WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos)
0WWDT_RELOAD_WORD (0x00005AA5)
>WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
FWWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
OWWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
XWWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
`WWDT_GET_COUNTER() (WWDT->CNT)
kWWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)H=






..\..\..\Library\StdDriver\inc\wwdt.h


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..\..\..\Library\StdDriver\inc\wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
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6__MINI58SERIES_H__ 
|__CM0_REV 0x0201
}__NVIC_PRIO_BITS 2
~__Vendor_SysTickConfig 0
__MPU_PRESENT 0
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__FPU_PRESENT 0…
†
‡

‹ACMP_CTL_ACMPEN_Pos (0)
ŒACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
ŽACMP_CTL_ACMPIE_Pos (1)
�ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
‘ACMP_CTL_HYSSEL_Pos (2)
’ACMP_CTL_HYSSEL_Msk (0x1ul << ACMP_CTL_HYSSEL_Pos)
”ACMP_CTL_NEGSEL_Pos (4)
•ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
—ACMP_CTL_RTRGEN_Pos (8)
˜ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
šACMP_CTL_FTRGEN_Pos (9)
›ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
�ACMP_CTL_FILTSEL_Pos (20)
žACMP_CTL_FILTSEL_Msk (0xful << ACMP_CTL_FILTSEL_Pos)
 ACMP_CTL_POSSEL_Pos (29)
¡ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
£ACMP_STATUS_ACMPIF0_Pos (0)
¤ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
¦ACMP_STATUS_ACMPIF1_Pos (1)
§ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
©ACMP_STATUS_ACMPO0_Pos (2)
ªACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
¬ACMP_STATUS_ACMPO1_Pos (3)
­ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
¯ACMP_VREF_CRVCTL_Pos (0)
°ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
²ACMP_VREF_IREFSEL_Pos (7)
³ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos)
•ADC_DAT_RESULT_Pos (0)
–ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
˜ADC_DAT_OV_Pos (16)
™ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
›ADC_DAT_VALID_Pos (17)
œADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
žADC_CTL_ADCEN_Pos (0)
ŸADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
¡ADC_CTL_ADCIEN_Pos (1)
¢ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
¤ADC_CTL_HWTRGSEL_Pos (4)
¥ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
§ADC_CTL_HWTRGCOND_Pos (6)
¨ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ªADC_CTL_HWTRGEN_Pos (8)
«ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
­ADC_CTL_SWTRG_Pos (11)
®ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
°ADC_CHEN_CHEN0_Pos (0)
±ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
³ADC_CHEN_CHEN1_Pos (1)
´ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
¶ADC_CHEN_CHEN2_Pos (2)
·ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
¹ADC_CHEN_CHEN3_Pos (3)
ºADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
¼ADC_CHEN_CHEN4_Pos (4)
½ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
¿ADC_CHEN_CHEN5_Pos (5)
ÀADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
ÂADC_CHEN_CHEN6_Pos (6)
ÃADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
ÅADC_CHEN_CHEN7_Pos (7)
ÆADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
ÈADC_CHEN_CH7SEL_Pos (8)
ÉADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
ËADC_CMP0_ADCMPEN_Pos (0)
ÌADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
ÎADC_CMP0_ADCMPIE_Pos (1)
ÏADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ÑADC_CMP0_CMPCOND_Pos (2)
ÒADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ÔADC_CMP0_CMPCH_Pos (3)
ÕADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
×ADC_CMP0_CMPMCNT_Pos (8)
ØADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ÚADC_CMP0_CMPDAT_Pos (16)
ÛADC_CMP0_CMPDAT_Msk (0x3fful << ADC_CMP0_CMPDAT_Pos)
ÝADC_CMP1_ADCMPEN_Pos (0)
ÞADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
àADC_CMP1_ADCMPIE_Pos (1)
áADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
ãADC_CMP1_CMPCOND_Pos (2)
äADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
æADC_CMP1_CMPCH_Pos (3)
çADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
éADC_CMP1_CMPMCNT_Pos (8)
êADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
ìADC_CMP1_CMPDAT_Pos (16)
íADC_CMP1_CMPDAT_Msk (0x3fful << ADC_CMP1_CMPDAT_Pos)
ïADC_STATUS_ADIF_Pos (0)
ðADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
òADC_STATUS_ADCMPF0_Pos (1)
óADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_S
CLK_CLKSEL1_PWMCH01SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH01SEL_Pos)
‚
CLK_CLKSEL1_PWMCH23SEL_Pos (30)
ƒ
CLK_CLKSEL1_PWMCH23SEL_Msk (0x3ul << CLK_CLKSEL1_PWMCH23SEL_Pos)
…
CLK_CLKDIV_HCLKDIV_Pos (0)
†
CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
ˆ
CLK_CLKDIV_UARTDIV_Pos (8)
‰
CLK_CLKDIV_UARTDIV_Msk (0xful << CLK_CLKDIV_UARTDIV_Pos)
‹
CLK_CLKDIV_ADCDIV_Pos (16)
Œ
CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
Ž
CLK_CLKSEL2_CLKOSEL_Pos (2)
�
CLK_CLKSEL2_CLKOSEL_Msk (0x3ul << CLK_CLKSEL2_CLKOSEL_Pos)
‘
CLK_CLKSEL2_PWMCH45SEL_Pos (4)
’
CLK_CLKSEL2_PWMCH45SEL_Msk (0x3ul << CLK_CLKSEL2_PWMCH45SEL_Pos)
”
CLK_CLKSEL2_WWDTSEL_Pos (16)
•
CLK_CLKSEL2_WWDTSEL_Msk (0x3ul << CLK_CLKSEL2_WWDTSEL_Pos)
—
CLK_PLLCTL_FBDIV_Pos (0)
˜
CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
š
CLK_PLLCTL_INDIV_Pos (9)
›
CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
�
CLK_PLLCTL_OUTDIV_Pos (14)
ž
CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
 
CLK_PLLCTL_PD_Pos (16)
¡
CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
£
CLK_PLLCTL_BP_Pos (17)
¤
CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
¦
CLK_PLLCTL_OE_Pos (18)
§
CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
©
CLK_PLLCTL_PLLSRC_Pos (19)
ª
CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
¬
CLK_CLKOCTL_FREQSEL_Pos (0)
­
CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
¯
CLK_CLKOCTL_CLKOEN_Pos (4)
°
CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
²
CLK_CLKOCTL_DIV1EN_Pos (5)
³
CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
þFMC_ISPCTL_ISPEN_Pos (0)
ÿFMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
�FMC_ISPCTL_BS_Pos (1)
‚FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
„FMC_ISPCTL_SPUEN_Pos (2)
…FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos)
‡FMC_ISPCTL_APUEN_Pos (3)
ˆFMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
ŠFMC_ISPCTL_CFGUEN_Pos (4)
‹FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
�FMC_ISPCTL_LDUEN_Pos (5)
ŽFMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
�FMC_ISPCTL_ISPFF_Pos (6)
‘FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
“FMC_ISPADDR_ISPADDR_Pos (0)
”FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
–FMC_ISPDAT_ISPDAT_Pos (0)
—FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
™FMC_ISPCMD_CMD_Pos (0)
šFMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
œFMC_ISPTRG_ISPGO_Pos (0)
�FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
ŸFMC_DFBA_DFBA_Pos (0)
 FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
¢FMC_FATCTL_FOM_Pos (4)
£FMC_FATCTL_FOM_Msk (0x7ul << FMC_FATCTL_FOM_Pos)
¥FMC_ISPSTS_ISPBUSY_Pos (0)
¦FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
¨FMC_ISPSTS_CBS_Pos (1)
©FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
«FMC_ISPSTS_ISPFF_Pos (6)
¬FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
®FMC_ISPSTS_VECMAP_Pos (9)
¯FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
±FMC_ISPSTS_SCODE_Pos (31)
²FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos)
¡GP_MODE_MODE0_Pos (0)
¢GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¤GP_MODE_MODE1_Pos (2)
¥GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
§GP_MODE_MODE2_Pos (4)
¨GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ªGP_MODE_MODE3_Pos (6)
«GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
­GP_MODE_MODE4_Pos (8)
®GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
°GP_MODE_MODE5_Pos (10)
±GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
³GP_DINOFF_DINOFF0_Pos (16)
´GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
¶GP_DINOFF_DINOFF1_Pos (17)
·GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
¹GP_DINOFF_DINOFF2_Pos (18)
ºGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
¼GP_DINOFF_DINOFF3_Pos (19)
½GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
¿GP_DINOFF_DINOFF4_Pos (20)
ÀGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÂGP_DINOFF_DINOFF5_Pos (21)
ÃGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÅGP_DINOFF_DINOFF6_Pos (22)
ÆGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÈGP_DINOFF_DINOFF7_Pos (23)
ÉGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ËGP_DOUT_DOUT0_Pos (0)
ÌGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ÎGP_DOUT_DOUT1_Pos (1)
ÏGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ÑGP_DOUT_DOUT2_Pos (2)
ÒGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ÔGP_DOUT_DOUT3_Pos (3)
ÕGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
×GP_DOUT_DOUT4_Pos (4)
ØGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ÚGP_DOUT_DOUT5_Pos (5)
ÛGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ÝGP_DOUT_DOUT6_Pos (6)
ÞGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
àGP_DOUT_DOUT7_Pos (7)
áGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ãGP_DATMSK_DATMSK0_Pos (0)
äGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
æGP_DATMSK_DATMSK1_Pos (1)
çGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
éGP_DATMSK_DATMSK2_Pos (2)
êGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ìGP_DATMSK_DATMSK3_Pos (3)
íGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
ïGP_DATMSK_DATMSK4_Pos (4)
ðGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
òGP_DATMSK_DATMSK5_Pos (5)
óGP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
õGP_DATMSK_DATMSK6_Pos (6)
öGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
øGP_DATMSK_DATMSK7_Pos (7)
ùGP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
ûGP_PIN_PIN0_Pos (0)
üGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN
¦]§]¨]
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..\..\..\Library\Device\Nuvoton\Mini58Series\Include\..\..\..\Library\CMSIS\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\Library\StdDriver\inc\Mini58Series.h
core_cm0.hsystem_Mini58Series.h
stdint.hsys.hclk.hacmp.hadc.hfmc.hgpio.hi2c.hpwm.hspi.htimer.huart.hwdt.hwwdt.h

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__DRV_SPI_H 
rfspi_pan159_irq() P52
rfspi_pan159_cs(level) (P01=(level))
rfspi_ce(v) xn297l_write_reg(CE_FSPI_ON|(v), 0)
rfspi_irq rfspi_pan159_irq
rfspi_cs rfspi_pan159_cs
rfspi_init rfspi_pan159_init
rfspi_rwc rfspi_pan159_rwc
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*__CORE_CMINSTR_H 5`V






..\..\..\Library\CMSIS\Include\core_cmInstr.h
cmsis_armcc.h


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..\..\..\Library\CMSIS\Include\core_cmInstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
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*__CORE_CMFUNC_H 5`U






..\..\..\Library\CMSIS\Include\core_cmFunc.h
cmsis_armcc.h


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..\..\..\Library\CMSIS\Include\core_cmFunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil
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*__CORE_CM0_H_GENERIC ,
J__CM0_CMSIS_VERSION_MAIN (0x04U)
K__CM0_CMSIS_VERSION_SUB (0x1EU)
L__CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB )
O__CORTEX_M (0x00U)
S__ASM __asm
T__INLINE __inline
U__STATIC_INLINE static __inline
|__FPU_USED 0U£
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__CORE_CM0_H_DEPENDANT 
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__I volatile const
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__IOM volatile
…APSR_N_Pos 31U
†APSR_N_Msk (1UL << APSR_N_Pos)
ˆAPSR_Z_Pos 30U
‰APSR_Z_Msk (1UL << APSR_Z_Pos)
‹APSR_C_Pos 29U
ŒAPSR_C_Msk (1UL << APSR_C_Pos)
ŽAPSR_V_Pos 28U
�APSR_V_Msk (1UL << APSR_V_Pos)
 IPSR_ISR_Pos 0U
¡IPSR_ISR_Msk (0x1FFUL )
¸xPSR_N_Pos 31U
¹xPSR_N_Msk (1UL << xPSR_N_Pos)
»xPSR_Z_Pos 30U
¼xPSR_Z_Msk (1UL << xPSR_Z_Pos)
¾xPSR_C_Pos 29U
¿xPSR_C_Msk (1UL << xPSR_C_Pos)
ÁxPSR_V_Pos 28U
ÂxPSR_V_Msk (1UL << xPSR_V_Pos)
ÄxPSR_T_Pos 24U
ÅxPSR_T_Msk (1UL << xPSR_T_Pos)
ÇxPSR_ISR_Pos 0U
ÈxPSR_ISR_Msk (0x1FFUL )
ÚCONTROL_SPSEL_Pos 1U
ÛCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
“SCB_CPUID_IMPLEMENTER_Pos 24U
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–SCB_CPUID_VARIANT_Pos 20U
—SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
™SCB_CPUID_ARCHITECTURE_Pos 16U
šSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
œSCB_CPUID_PARTNO_Pos 4U
�SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ŸSCB_CPUID_REVISION_Pos 0U
 SCB_CPUID_REVISION_Msk (0xFUL )
£SCB_ICSR_NMIPENDSET_Pos 31U
¤SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
¦SCB_ICSR_PENDSVSET_Pos 28U
§SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
©SCB_ICSR_PENDSVCLR_Pos 27U
ªSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
¬SCB_ICSR_PENDSTSET_Pos 26U
­SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
¯SCB_ICSR_PENDSTCLR_Pos 25U
°SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
²SCB_ICSR_ISRPREEMPT_Pos 23U
³SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
µSCB_ICSR_ISRPENDING_Pos 22U
¶SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
¸SCB_ICSR_VECTPENDING_Pos 12U
¹SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
»SCB_ICSR_VECTACTIVE_Pos 0U
¼SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
¿SCB_AIRCR_VECTKEY_Pos 16U
ÀSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ÂSCB_AIRCR_VECTKEYSTAT_Pos 16U
ÃSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
ÅSCB_AIRCR_ENDIANESS_Pos 15U
ÆSCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ÈSCB_AIRCR_SYSRESETREQ_Pos 2U
ÉSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
ËSCB_AIRCR_VECTCLRACTIVE_Pos 1U
ÌSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ÏSCB_SCR_SEVONPEND_Pos 4U
ÐSCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
ÒSCB_SCR_SLEEPDEEP_Pos 2U
ÓSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
ÕSCB_SCR_SLEEPONEXIT_Pos 1U
ÖSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
ÙSCB_CCR_STKALIGN_Pos 9U
ÚSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
ÜSCB_CCR_UNALIGN_TRP_Pos 3U
ÝSCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
àSCB_SHCSR_SVCALLPENDED_Pos 15U
áSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ùSysTick_CTRL_COUNTFLAG_Pos 16U
úSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
üSysTick_CTRL_CLKSOURCE_Pos 2U
ýSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ÿSysTick_CTRL_TICKINT_Pos 1U
€SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
‚SysTick_CTRL_ENABLE_Pos 0U
ƒSysTick_CTRL_ENABLE_Msk (1UL )
†SysTick_LOAD_RELOAD_Pos 0U
‡SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ŠSysTick_VAL_CURRENT_Pos 0U
‹SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ŽSysTick_CALIB_NOREF_Pos 31U
�SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALI
..\..\..\Library\CMSIS\Include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\Terry\Desktop\PAN159-Template\SampleCode\Template\Keil*›!_reserved0Y
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__SYSTEM_MINI58SERIES_H__ 
__XTAL12M (12000000UL)
__XTAL32K (32768UL)
__IRC10K (10000UL)
__XTAL __XTAL12M
__HXT __XTAL
 __HIRC (22118400UL)lb






..\..\..\Library\Device\Nuvoton\Mini58Series\Include\system_Mini58Series.h


4